In recent years, an AC plasma display device which performs a surface discharge has been put into practical use as a flat image display device, and it has been widely used as an image display device of a personal computer, a workstation and others, a wall-hung flat television, and a device for displaying advertisements, information and others. For example, in a recent three-electrode surface-discharge type plasma display device, since the discharge intensity becomes higher and the background light emission is increased when a reset is performed with rectangular waves, the reset is performed by obtuse waves so as to reduce the background light emission and improve the contrast.
However, even the plasma display device using such obtuse-wave reset is not satisfactory, and it is desired to further reduce the background light emission so as to further improve the contrast in order to provide higher-quality video images.
Conventionally, a plasma display device which performs a surface discharge has been put into practical use as a flat image display device, in which all pixels on a screen simultaneously emit light in accordance with display data. The plasma display device which performs a surface discharge has a structure in which a pair of electrodes are formed in an inner surface of a front glass substrate, and a rare gas is sealed therein. When a voltage is applied between the electrodes, the surface discharge occurs on the surfaces of a dielectric layer and a protection layer formed on the electrode surfaces, thereby generating ultraviolet rays. The inner surface of a rear glass substrate is coated with phosphors of three primary colors, red (R), green (G), and blue (B), and the color display is carried out when the phosphors are excited by the ultraviolet rays so as to emit light.
FIG. 1 is a diagram schematically showing an example of a conventional plasma display panel, in which a three-electrode surface-discharge AC plasma display panel is shown.
In FIG. 1, a reference numeral 10 denotes a plasma display panel (PDP), 11 denotes a front-side substrate (front substrate), 12 denotes a transparent electrode for an X electrode, 13 denotes a bus electrode for the X electrode, 14 denotes a transparent electrode for a Y electrode, 15 denotes a bus electrode for the Y electrode, 16 denotes a rear-side substrate (rear substrate), 17 denotes an address electrode, 18 denotes a barrier rib (rib), and 19R, 19G, and 19B denote phosphor layers. Note that, in the actual PDP 10, a dielectric layer and a protection layer are provided on the X electrode and the Y electrode, and a dielectric layer is provided on the address electrode. Further, the space between the front-side substrate 11 in which the X electrodes (12, 13) and the Y electrodes (14, 15) are provided and the rear-side substrate 16 in which the address electrodes 17 are provided is filled with a discharge gas such as a mixed gas of neon and xenon, so that the discharge space at an intersecting part of the X and Y electrodes and the address electrode forms one discharge cell.
FIG. 2 is a diagram showing an example of a grayscale driving sequence in a conventional plasma display device.
As shown in FIG. 2, in the grayscale driving sequence in the plasma display device, one field (frame) is comprised of a plurality of sub-fields (sub-frames) SF1 to SFn respectively having predetermined weights of luminance, and desired grayscale display is performed by the combination of the sub-fields. Specifically, as the plurality of sub-fields, for example, eight sub-fields SF1 to SF8 having luminance weights in powers of 2 (ratio of the times of sustain discharge is 1:2:4:8:16:32:64:128) are used so as to perform the display of 256 grayscales.
FIG. 3 is a diagram for describing a driving method of the conventional plasma display device.
As shown in FIG. 2 and FIG. 3, each of the sub-fields (for example, SF1 to SF8) is comprised of a reset period (initialization process) TR in which wall charges (charging state) of all cells in the display region are made uniform, an address period (address process) TA in which wall charges are formed in the cells to be lit so as to select the lighting cells, and a sustain period (display process) TS in which the lighting cells in which the wall charges are formed are discharged (lit) as many times depending on the luminance thereof. The cells are lit in accordance with the luminance of display of each sub-field. For example, the display of one field is performed through the displays of the eight sub-fields (SF1 to SF8).
More specifically, in the reset period TR, first, discharges are generated in all cells by pulses P1 so as to write wall charges thereto, and discharges which remove the wall charges of all the cells are generated by subsequent pulses P2 so as to adjust the charging state to zero. In this event, in the reset period TR, obtuse waves (obtuse-wave reset) in which the voltage gradually varies along with the time course are used as the pulses P1 applied to the Y electrodes for generating the discharges in all the cells, so as to reduce the background light emission and improve the contrast.
Furthermore, in the address period TA, scan pulses SCP are sequentially applied to the Y electrodes (14, 15), and at the same time, address pulses ADP are applied to the cells to be lit based on display data, so as to cause the address discharge and form the wall charges.
Then, in the sustain period TS, sustain discharge pulses (display discharge pulses) STP are applied to the X electrodes and Y electrodes (display electrodes), and only the cells in which the wall charges have been formed by the address discharge are lit. The luminance of the cells is controlled depending on the number of times of the sustain discharge pulses.
FIG. 4 is a block diagram schematically showing the entire structure of an example of a conventional plasma display device, in which an example of a plasma display device 100 using the PDP 10 shown in FIG. 1 is schematically shown.
The plasma display device 100 has the PDP 10, an X driver 32, a Y driver 33, and an address driver 34 for driving the cells of the PDP 10, and a control circuit 31 for controlling the drivers. Field data Df which is multi-valued image data representing luminance levels of three colors of R, G, and B and various synchronization signals (clock signal CLK, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync) from external devices such as a TV tuner and a computer are inputted to the control circuit 31. In accordance with the field data Df and the various synchronization signals, the control circuit 31 outputs control signals suitable for the drivers 32 to 34 so as to perform predetermined image displays.
The Y driver 33 controls the Y electrodes and has a scan driver (scan driver LSI) 331 and a common driver 332. Also, the X driver 32 controls the X electrodes and has a common driver 320.
Conventionally, in order to prevent generation of bright defects and the like in a dark screen even when intervals between discharge cells are narrow and to reliably execute the reset discharge in a bright screen, a method of driving a plasma display device has been proposed, in which the ratio of light-emitting pixels in one screen is detected and inputted to a control pulse power supply, and in accordance with the ratio of light-emitting pixels, sub-field reset voltages are reduced in the image of low ratio and sub-field reset voltages are increased in the image of high ratio (for example, see Japanese Patent Application Laid-Open Publication No. 2000-029431 (Patent Document 1)).
Also, conventionally, in order to reduce the background light emission of an ALIS panel to improve the darkroom contrast, a method of driving a plasma display device has been proposed, in which at least a write discharge step and an elimination discharge step are provided in a reset period, and voltages in the write discharge step are varied at least in a part of sub-fields (for example, see Japanese Patent Application Laid-Open Publication No. 2003-050562 (Patent Document 2)).